1. Field of the Invention
The present invention relates to a driving apparatus of a plasma display panel (PDP).
2. Discussion of the Related Art
Flat panel displays, such as liquid crystal displays (LCDs), field emission displays (FEDs) and PDPs, are being actively developed. PDPs have high luminance, high luminous efficiency and a wide viewing angle. Accordingly, they are being highlighted as the primary substitute for conventional cathode ray tubes (CRTs) for large-screen displays of more than 40 inches.
PDPs use plasma generated by gas discharge to display characters or images, and depending on their size, they may have several thousands to millions of pixels. PDPs may be classified as direct current (DC) type and alternating current (AC) type according to voltage driving waveforms and discharge cell structures.
The AC PDP's electrodes are covered with a dielectric layer, which protects the electrodes during discharge. Therefore, the AC PDP has a longer lifespan than the DC PDP.
A typical AC PDP includes scan electrodes and sustain electrodes formed in parallel on one main surface of the PDP, and address electrodes, orthogonally arranged to the scan and sustain electrodes, are formed on the PDP's other main surface.
In general, a typical AC PDP driving method uses a reset period, an address period, and a sustain period.
During the reset period, cells are reset so as to readily perform the subsequent address operation. During the address period, cells that are to be turned on are selected, and an address discharge accumulates wall charges in the turned-on cells (i.e., addressed cells). During the sustain period, images are displayed by applying a sustain discharge voltage pulse to the addressed cells.
As used herein, “wall charges” refers to charges that accumulate on the electrodes and are formed on the wall (e.g., dielectric layer) of the discharge cells. The wall charges may not actually contact the electrodes because they are covered by a dielectric layer. However, for ease of description, the wall charges may be described herein as being “formed on”, “stored on” or “accumulated on” the electrodes.
U.S. Pat. Nos. 4,866,349 and 5,081,400 disclose a sustain discharge circuit (or a power recovery circuit) that may recover inactive power for charging and discharging a panel capacitor. The power recovery circuit may charge and discharge the panel capacitor using an inductor and an LC resonance.
FIG. 1 shows a conventional power recovery circuit.
As shown in FIG. 1, the power recovery circuit includes a sustain discharge path having sustain discharge switches Ys, Yg, Xs and Xg, and charge and discharge paths for charging electric charges between the panel capacitor Cp and the power recovery capacitors Cyr and Cxr. A Y electrode may be charged through a path of a switch Yr, a diode YDr and an inductor Ly and may be discharged through a path of the inductor Ly, a diode YDf and a switch Yf. Similarly, an X electrode may be charged through a path of a switch Xr, a diode XDr and an inductor Lx and may be discharged through a path of the inductor Lx, a diode XDf and a switch Xf.
However, the inductor and parasite capacitors of the switches may resonate, thereby generating a distorted waveform such as an overshoot and an undershoot. Accordingly, in order to suppress the distorted waveform and reduce a withstand voltage of the switches, the power recovery circuit further includes clamping diodes YDCH, XDCH, YDCL and XDCL for preventing a voltage at the front stage of the inductors Ly and Lx from rising above a fixed voltage Vs or falling below 0 V.
Additionally, in order to overcome electromagnetic interference (EMI) problems and noise due to the resonance between inductors and parasite capacitors, low pass filters (LPF), such as EMI beads, for suppressing high frequency components may be inserted between diodes.
However, these LPFs may be provided on the same path as the clamping diodes, which may lead to poor functionality of the clamping diodes.